BENGALURU: The Indian Institute of Science (IISc) has partnered with Samsung Semiconductor India Analysis (SSIR), a subsidiary of Samsung Electronics, to advertise analysis and improvement (R&D) within the subject of on-chip Electrostatic Discharge (ESD) — sudden and momentary movement of electrical present between two electrically charged objects— safety.
“The partnership seeks to construct cutting-edge ESD gadget options to guard ultra-high-speed serial interfaces in superior Built-in Circuits (ICs) and system-on-chip (SoC) merchandise,” IISc mentioned.
The associated analysis will likely be carried out by Prof Mayank Shrivastava’s group at IISc’s division of digital methods engineering (DESE) and options arising from this analysis will likely be deployed in Samsung’s superior course of nodes.
“ICs and SoCs are important for virtually any system, from small to massive, that we see round us, however they’re very delicate to ESD failures, particularly these developed utilizing superior nanoscale CMOS (Complementary Metallic Oxide Semiconductor) applied sciences. The vast majority of IC chip failures and subject returns are attributed to ESD failures,” IISc mentioned, explaining the context for such R&D.
Arguing that ESD associated know-how is a uncommon experience and industries holding the artwork of designing ESD safety units and interface ideas lead the market, IISc added that subsequently, R&D in ESD know-how for extremely dependable interfaces and SoCs that function at low energy and excessive velocity is an integral a part of the semiconductor innovation effort.
IISc is likely one of the few institutes on the planet main ESD gadget analysis. “We’re glad to companion with IISc to spice up semiconductor innovation and envisage growing ESD information together with experience obtainable in IISc. Our aim can also be to extend capability constructing via coaching programmes on the postgraduate degree, opening up alternatives for college students to pursue {industry} internships, and encourage entrepreneurial ventures by younger researchers,” IISc quoted SSIR MD Balajee Sowrirajan as having mentioned.
Prof Govindan Rangarajan, director, IISc, mentioned the institute was excited to collaborate with SSIR within the essential space of superior nanoelectronics gadget analysis and that the partnership reinforces the institute’s dedication to strengthen industry-academia engagements that may make a big affect within the coming years.
“We’ve been collaborating extensively with semiconductor industries worldwide on superior nanoelectronics applied sciences, together with options to ESD reliability threats to superior SoCs. We now have carried out each basic and utilized analysis on ESD safety units, with a powerful emphasis on creating sensible options for the semiconductor {industry} in a spread of know-how nodes,” mentioned Prof Mayank Shrivastava, who heads the MSDLab, and will likely be main this collaborative effort.
“The partnership seeks to construct cutting-edge ESD gadget options to guard ultra-high-speed serial interfaces in superior Built-in Circuits (ICs) and system-on-chip (SoC) merchandise,” IISc mentioned.
The associated analysis will likely be carried out by Prof Mayank Shrivastava’s group at IISc’s division of digital methods engineering (DESE) and options arising from this analysis will likely be deployed in Samsung’s superior course of nodes.
“ICs and SoCs are important for virtually any system, from small to massive, that we see round us, however they’re very delicate to ESD failures, particularly these developed utilizing superior nanoscale CMOS (Complementary Metallic Oxide Semiconductor) applied sciences. The vast majority of IC chip failures and subject returns are attributed to ESD failures,” IISc mentioned, explaining the context for such R&D.
Arguing that ESD associated know-how is a uncommon experience and industries holding the artwork of designing ESD safety units and interface ideas lead the market, IISc added that subsequently, R&D in ESD know-how for extremely dependable interfaces and SoCs that function at low energy and excessive velocity is an integral a part of the semiconductor innovation effort.
IISc is likely one of the few institutes on the planet main ESD gadget analysis. “We’re glad to companion with IISc to spice up semiconductor innovation and envisage growing ESD information together with experience obtainable in IISc. Our aim can also be to extend capability constructing via coaching programmes on the postgraduate degree, opening up alternatives for college students to pursue {industry} internships, and encourage entrepreneurial ventures by younger researchers,” IISc quoted SSIR MD Balajee Sowrirajan as having mentioned.
Prof Govindan Rangarajan, director, IISc, mentioned the institute was excited to collaborate with SSIR within the essential space of superior nanoelectronics gadget analysis and that the partnership reinforces the institute’s dedication to strengthen industry-academia engagements that may make a big affect within the coming years.
“We’ve been collaborating extensively with semiconductor industries worldwide on superior nanoelectronics applied sciences, together with options to ESD reliability threats to superior SoCs. We now have carried out each basic and utilized analysis on ESD safety units, with a powerful emphasis on creating sensible options for the semiconductor {industry} in a spread of know-how nodes,” mentioned Prof Mayank Shrivastava, who heads the MSDLab, and will likely be main this collaborative effort.
